Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a refresh control circuit and method for a semiconductor memory device.
A memory device, for example, a Dynamic Random Access Memory (DRAM) device, includes a plurality unit cells each of which has one transistor and one capacitor, and data is preliminarily stored in the capacitor. However, since a capacitor formed over a semiconductor substrate is not completely electrically disconnected from its surroundings in a memory device, the data stored in the capacitor may be discharged, and thus, the data may not be retained. In short, leakage current occurs and data of a memory cell may be damaged. To address the problem, the memory device periodically performs a refresh operation to retain the charge which was stored in the capacitor.
A memory device having a refresh operation mode performs a refresh operation while sequentially varying the internal address based on an external command. In other words, when the memory device enters the refresh operation mode based on an external command, a word line of a memory cell is selected according to a row address, which sequentially increases at a predetermined period. The charge stored in the capacitor corresponding to the selected word line is amplified by a sense amplifier and then stored again in the capacitor. Through a series of refresh processes, the stored data is retained without being damaged.
The refresh operation is largely divided into a self-refresh operation and an auto refresh operation. According to the self-refresh operation, an external controller sends a refresh initialization signal and a device performs a refresh operation until the device receives a refresh termination signal. According to the auto refresh operation, an external controller sends a refresh command during a normal operation and a device performs a refresh operation accordingly. Herein, both the self-refresh operation and the auto refresh operation are performed as an internal counter generates an address after the device receives a command and the address sequentially increases whenever the device receives a request.
According to the self-refresh operation, the refresh operation is performed periodically according to a period decided internally. Herein, a period of recharging a capacitor is referred to as a refresh period and it is decided based on a condensing capacity and extermination time of a cell.
According to the auto refresh operation, where a semiconductor device has a refresh cycle of approximately 4 k/64 ms, a counter sequentially refreshes all cells internally when 4096 auto refresh commands are received within 64 milliseconds (ms).
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device for controlling an auto refresh operation.
As shown in the drawing, the conventional semiconductor memory device 100 for controlling a refresh operation includes a command generator 110, a refresh counter 120, a row address decoder 130, and a cell array 140.
The command generator 110 decodes external commands CSB, RASB, CASB and WEB inputted from the outside of the semiconductor memory device in response to a clock CLK to generate internal commands REF and ACT. Herein, the external command “CSB” denotes a chip selection signal, and the external command “RASB” denotes a row address strobe signal. The external command “CASB” denotes a column address strobe signal, and the external command “WEB” denotes a write enable signal. Also, the internal command “REF” denotes a refresh signal, and the internal command “ACT” denotes an active signal.
The refresh counter 120 counts the refresh signal REF in response to the active signal ACT outputted from the command generator 110, and outputs a refresh address RA<0:N> so that all the word lines in the cell array 140 are sequentially accessed.
The row address decoder 130 decodes the refresh address RA<0:N>, generated in the refresh counter 120 during a refresh operation mode, and generates a row address selection signal BX_ADD for selecting a row address to perform a refresh operation.
The cell array 140 retains a stored charge by performing a refresh operation based on the row address selection signal BX_ADD, and thus, prevents data from being lost.
Hereafter, a conventional method for controlling a refresh operation of a semiconductor memory device is described with reference to FIG. 1.
First, the command generator 110 enables the active signal ACTMD after entering an active mode. Herein, the auto refresh counter 120 counts the refresh signal REF in response to the active signal ACT, outputted from the command generator 110, and outputs the refresh address RA<0:N>. The row address decoder 130 decodes the refresh address RA<0:N>, outputted from the auto refresh counter 120, and generates the row address selection signal BX_ADD for selecting a row address to perform a refresh operation. Therefore, the cell array 140 retains the stored charge by performing the refresh operation in response to the row address selection signal BX_ADD and prevents the data from being lost. Herein, the refresh operation is performed for one refresh row cycle time tRFC.
The method for performing an auto refresh operation based on an external command, which is described above, may not only apply a predetermined retention time to all cells constantly, but may also vary the amount of generated noise by changing the sequence refresh addresses. Therefore, it is useful for cell screening.
However, the conventional auto refresh operation is performed at a period determined based on an average retention time determined under the assumption that all cells have the same retention characteristic. Therefore, although a cell which does not have sufficient retention time needs to perform the refresh operation at a shorter refresh period than the determined period, the conventional refresh method performs the refresh operation according to the period determined based on the average retention time, and thus, data are lost.